Electronic clock generation classically relies on a reference oscillator based on an external crystal that is optionally multiplied and/or divided to generate the required clock. The key specifications of a clock, other than its target frequency, are frequency accuracy and stability. Frequency accuracy is the ability to maintain the target frequency across supply and temperature and is usually represented as drift from the target frequency in percent or parts per million (ppm). Long term stability, is impacted by the close-in phase noise of the oscillator. An oscillator using a high-Q element typically has a low phase noise profile, and thus good frequency stability, and is less sensitive to variations in oscillator amplifier gain, which is dependent on supply and temperature.
For example, crystal oscillators (XOs) are high-Q oscillators that provide excellent frequency stability and frequency accuracy across supply and temperature stemming from the very high quality factor (Q) of the crystal. However, not all resonators, including crystals, have satisfactory performance across temperature, thus the need for extra circuitry and techniques to decrease and/or compensate for shifts in frequency due to temperature. A temperature compensated crystal oscillator (TCXO) typically incorporates extra devices that have temperature dependence to negate the temperature dependence of the crystal. The overall outcome is an oscillation frequency with low temperature dependence.
However, the ever increasing complexity of electronic systems due to requirements of supporting multiple standards, increased functionality, higher data rates and increased memory in a smaller size and at a lower cost is pushing designers to increase the integration level through the development of Systems on Chip (SoC) in deep submicron Complimentary MOS (CMOS) technologies to benefit from the increased gate density. Reference clocks incorporating crystal oscillators have not managed to scale or integrate due to the bulky nature of crystals, thus limiting the size and cost reduction possible for electronic systems.
Recent efforts in using high-Q MEMS resonators and Film Bulk Acoustic Resonators (FBARs) have illustrated possibilities of integrating a high-Q element and Application Specific Integrated Circuits (ASIC) in the same package. However, packaging induced stress and its impact on performance still remains as a challenging obstacle, since the high-Q element may require special packages and/or calibration that are not practical for SoCs. The stress may change the temperature behavior of the resonator, possibly resulting in large frequency shifts and accelerated aging. Therefore, special assembly and packaging techniques are typically required to mitigate such effects, which increase the cost of producing such clocks. Similar problems may be encountered by any resonator that is dependent on the mechanical properties of the resonator material, which require careful design and manufacturing procedures and processes.
Design requirements for applications such as USB and SATA, which do not require superior frequency accuracy and stability, can be satisfied using oscillators with relatively low-Q elements available in a CMOS process which can have adequate phase noise profiles generating good jitter performance. Current trials include the use of ring oscillators, relaxation oscillators and LC oscillators. However, the reported frequency accuracy of these implementations suffers from large drift across supply and temperature, making them ineffective for applications requiring precise accuracy and stability. A mitigation to reduce the drift across temperature requires trimming across temperature which is neither cost effective nor practical for SoCs.
Therefore, an integrated solution that relies on existing optimized process steps in CMOS technology and that satisfies frequency stability and jitter requirements would be of great value. LC tank oscillators operating at the tank temperature-null phase to achieve highly stable output frequency have been described in U.S. Pat. No. 8,072,281, incorporated herein by reference. Techniques and circuits described herein include improvements and extensions that take advantage of the temperature-null phase.